A method for implementing address translation unit for use in solid-state drive controllers

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Abstract

The paper proposes a method for implementing the translation of logical addresses of host requests of stored data into physical addresses of data located in an array of non-volatile NAND Flash memory. The main limitations of working with NAND Flash memory are described, and a set of mechanisms for solving the problem of address translation is proposed. Additionally, optimization methods of the translation table cells are described to achieve high optimization of interaction with the memory buffer allocated for storing the address translation table. The proposed methods and the described features can be used in the development of address translation units of modern high-performance solid-state drive (SSD) controllers with high logical capacity.

About the authors

K. D. Lyubavin

Kraftway Corporation PLC JSC

Author for correspondence.
Email: klyubavin@kraftway.ru

Lead Engineer, Department of Logical Design

Russian Federation, Moscow, 129626

D. V. Telpukhov

AlphaCHIP LLC

Email: telpukhov@alphachip.ru

Dr. Sc., Deputy Director General for Science

Russian Federation, Zelenograd, Moscow

References

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