The concurrent error-detection systems organization based on the Boolean complement method with the preliminary transformation of operating functions into check vectors of Berger codes
- Authors: Efanov D.V.1,2,3, Saposhnikov V.V.4, Saposhnikov V.V.4
-
Affiliations:
- Scientific and Technical Center "Integrated Monitoring Systems" LLC
- Peter the Great St. Petersburg Polytechnic University
- Russian University of Transport
- Emperor Alexander I St. Petersburg State Transport University
- Issue: Vol 27, No 6 (2021)
- Pages: 306-313
- Section: Digital processing of signals and images
- Published: 15.06.2021
- URL: https://journals.eco-vector.com/1684-6400/article/view/702857
- DOI: https://doi.org/10.17587/it.27.306-313
- ID: 702857
Cite item
Full Text
Abstract
The article describes a new way of concurrent error-detection (CED) systems organization using the Boolean complement method, which involves the use of pre-compression of signals from the diagnostic object using encoders of classical sum codes (Berger codes). Control of compressed signals is carried out using the constant-weight “1-out-of-4” code. In comparison with the known methods of the CED systems organization, it is possible to implement a self-checking digital device using one such circuit, and this significantly reduces the structural redundancy. The article suggests using the encoders of modified Berger codes with improved error detection characteristics as a compression scheme.
About the authors
D. V. Efanov
Scientific and Technical Center "Integrated Monitoring Systems" LLC; Peter the Great St. Petersburg Polytechnic University; Russian University of Transport
Author for correspondence.
Email: TrES-4b@yandex.ru
D. Sc., Associate Professor
Russian Federation, St. Petersburg; St. Petersburg; MoscowV. V. Saposhnikov
Emperor Alexander I St. Petersburg State Transport University
Email: port.at.pgups@gmail.com
D. Sc., Professor
Russian Federation, St. PetersburgV. V. Saposhnikov
Emperor Alexander I St. Petersburg State Transport University
Email: at.pgups@gmail.com
D. Sc., Associate Professor
Russian Federation, St. PetersburgReferences
- Fujiwara E. Code Design for Dependable Systems: Theory and Practical Applications, John Wiley & Sons, 2006, 720 p.
- Ubar R., Raik J., Vierhaus H.-T. Design and Test Technology for Dependable Systems-on-Chip (Premier Reference Source). Information Science Reference, Hershey New York, IGI Global, 2011, 578 p.
- Drozd A. V., Kharchenko V. S., Antoshchuk S. G., Drozd Yu. V., Drozd M. A., Sulima Yu. Yu. Objects and Methods of On-Line Testing for Safe Instrumentation and Control Systems, Kharkov, National Aerospace University "KhAI, 2012, 614 p. (in Russian).
- Hahanov V. Cyber Physical Computing for IoT-driven Services, New York, Springer International Publishing AG, 2018, 279 p., doi: 10.1007/978-3-319-54825-8.
- Sogomonyan E. S., Slabakov E. V. Self-checking devices and fault-tolerant systems, Radio & Svjaz`, Moscow, 208 p. (in Russian).
- Parkhomenko P. P., Sogomonyan E. S. Fundamentals of technical diagnostics (optimization of diagnostic algorithms, hardware, Moscow, Energoatomizdat, 1981, 320 p. (in Russian).
- Piestrak S. J. Design of Self-Testing Checkers for Unidirectional Error Detecting Codes, Wrolaw, Oficyna Wydawnicza Politechniki Wroclavskiej, 1995, 111 p.
- Abramovici M., Breuer M. A., Friedman A. D. Digital System Testing and Testable Design, New Jersey, IEEE Press, 1998, 652 p.
- Lala P. K. Principles of Modern Digital Design, New Jersey, John Wiley & Sons, 2007, 419 p.
- Sapozhnikov V. V., Sapozhnikov Vl. V., Efanov D. V. Sum codes for technical diagnostic systems. Volume 1: Classic Berger codes and their modifications, Moscow, Nauka, 2020, 383 p. (in Russian).
- Sapozhnikov V. V., Sapozhnikov Vl. V., Efanov D. V. Sum codes for technical diagnostic systems. Volume 2: Weighted codes with summation, Moscow, Nauka, 2021. 455 p. (in Russian).
- Saposhnikov Vl. V., Dmitriev A., Goessel M., Saposhnikov V. V. Self-Dual Parity Checking a New Method for on Line Testing, Proceedings of 14th IEEE VLSI Test Symposium, USA, Princeton, 1996, pp. 162—168.
- Goessel M., Ocheretny V., Sogomonyan E., Marienfeld D. New Methods of Concurrent Checking: Edition 1. Dordrecht: Springer Science + Business Media B. V., 2008, 184 p.
- Sen S. K., Roy S. S. An Optimized Concurrent Self-Checker Using Constraint-Don’t Cares and 1-out-of-4 Code, National Conference (AECDISC’2008) in Asansol Engineering College, held during 1—2 August 2008.
- Sen S. K. A Self-Checking Circuit for Concurrent Checking by 1-out-of-4 code with Design Optimization using Constraint Don’t Cares, National Conference on Emerging trends and advances in Electrical Engineering and Renewable Energy (NCEEERE’2010), Sikkim Manipal Institute of Technology, Sikkim, held during 22—24 December, 2010.
- Das D. K., Roy S. S., Dmitiriev A., Morozov A., Gossel M. Constraint Don’t Cares for Optimizing Designs for Concurrent Checking by 1-out-of-3 Codes, Proceedings of the 10th International Workshops on Boolean Problems, Freiberg, Germany, September, 2012, pp. 33—40.
- Pivovarov D. V. Organization of concurrent error-detection systems for combinational logic circuits based on the method of Boolean complement according to the constant-weight code "1-out-of-5", Avtomatika na Transporte, 2017, vol. 3, iss. 4, pp. 605—624 (in Russian).
- Efanov D. V., Sapozhnikov V. V., Sapozhnikov Vl. V., Pivovarov D. V. The Synthesis Conditions of Completely Self-Testing Embedded-Control Circuits Based on the Boolean Complement Method to the "1-out-of-m" Constant-Weight Code, Automatic Control and Computer Sciences, 2020, vol. 54, iss. 2, pp. 89—99. doi: 10.3103/S0146411620020042.
- Freiman C. V. Optimal Error Detection Codes for Completely Asymmetric Binary Channels, Information and Control, 1962, vol. 5, iss. 1, pp. 64—71. doi: 10.1016/S0019-9958(62)90223-1.
- Berger J. M. A Note on Error Detection Codes for Asymmetric Channels, Information and Control, 1961, vol. 4, iss. 1, pp. 68—73. doi: 10.1016/S0019-9958(61)80037-5.
- Efanov D., Sapozhnikov V., Sapozhnikov Vl., Osadchy G., Pivovarov D. Self-Dual Complement Method up to Constant-Weight Codes for Arrangement of Combinational Logical Circuits Concurrent Error-Detection Systems, Proceedings of 17th IEEE East-West Design & Test Symposium (EWDTS’2019), Batumi, Georgia, September 13—16, 2019, pp. 136—143, doi: 10.1109/EWDTS.2019.8884398.
- Pivovarov D. V. Construction of concurrent error-detection systems for multi-output combinational circuits by the Boolean complement method using constant-weight codes, Avtomatika na Transporte, 2018, vol. 4, iss. 1, pp. 131—149 (in Russian).
- Nikolos D. Self-Testing Embedded Two-Rail Checkers, Chapter 7 in On-Line Testing for VLSI, 1998, pp. 69—79. doi: 10.1007/978-1-4757-60-69-9_7.
- Sapozhnikov V. V., Sapozhnikov Vl. V., Efanov D. V. Synthesis of a built-in control circuit for multi-output combinational devices based on Boolean complement and signal compression, Izvestiya vuzov. Priborostroenie, 2020, vol. 63, iss. 7, pp. 581—597. DOI: 10.17586 / 0021-3454-2020-63-7-581-597 (in Russian).
- Efanov D. V., Sapozhnikov V. V., Sapozhnikov Vl. V., Osadchiy G. V. Synthesis of built-in control circuits based on the Boolean complement method with preliminary compression of signals of working functions, Bulletin of the Tomsk State University. Management, computer technology and informatics, 2021, iss. 1, pp. 97—115. doi: 10.17223/19988605/54/12 (in Russian).
- Efanov D. V., Sapozhnikov V. V., Sapozhnikov Vl. V. Organization of Testing of Combinational Devices Based on Boolean Complement to Constant-Weight "1-out-of-4" Code with Signal Compression, Automation and Computer Science, 2021, vol. 55, iss. 2, pp. 113—124. doi: 10.3103/S014641126102005X.
- Sapozhnikov V. V., Sapozhnikov Vl. V., Efanov D. V. Method of concurrent error-detection checking of combinational logical devices based on the code "2-out-of-4", Izvestiya vuzov. Priborostroenie, 2016, vol. 59, iss. 7, pp. 524—533, DOI: 10.17586/ 0021-3454-2016-59-7-524-533 (in Russian).
- Busaba F. Y., Lala P. K. Self-Checking Combinational Circuit Design for Single and Unidirectional Multibit Errors, Journal of Electronic Testing: Theory and Applications, 1994, vol. 5, iss. 5, pp. 19—28.
- Matrosova A., Levin I., Ostanin S. Survivable Self-Checking Sequential Circuits, Proceedings of 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’2001), USA, CA, San Francisco, October 24—26, 2001, pp. 395—402.
- Sogomonyan E. S., Gossel M. Design of Self-Testing and On-Line Fault Detection Combinational Circuits with Weakly Independent Outputs, Journal of Electronic Testing: Theory and Applications, 1993, vol. 4, iss. 4, pp. 267—281, DOI: 10.1007/ BF00971975.
Supplementary files

