The paper describes the method of increasing memory performance by reordering requests to memory controller. DDR SDRAM is organized in 8 or 16 banks. Each bank is independent from each other, but if the contiguous access requests go to the same bank, the old row in this bank precharge operation and activation of a new row operation have to be performed. If DDR SDRAM access has frequent open row conflicts in the banks, memory subsystem performance significantly decreases. To increase memory access bandwidth, we need to make data burst transfers as long as possible. However, for example, copying algorithms of the Debian Linux operation system use the burst length limited by the cacheline size. To avoid it, it is proposed to reorder read requests with write requests. The reordering control is being done with a state machine. This state machine delays write requests by a dedicated FIFO. Read requests are first processed. If the address dependence in the read and write requests is detected, those requests are sent to DDR SDRAM memory in order. After debugging on the simulator, this mechanism was implemented in a FPGA. The performance was measured on the data transfer cycles with and without requests reordering. Measurements on copying data using the Linux operating system show an increase in bandwidth up to 39 %.