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<article xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:ali="http://www.niso.org/schemas/ali/1.0/" article-type="oration" dtd-version="1.2" xml:lang="en"><front><journal-meta><journal-id journal-id-type="publisher-id">Informacionnye Tehnologii</journal-id><journal-title-group><journal-title xml:lang="en">Informacionnye Tehnologii</journal-title><trans-title-group xml:lang="ru"><trans-title>Информационные технологии</trans-title></trans-title-group></journal-title-group><issn publication-format="print">1684-6400</issn><publisher><publisher-name xml:lang="en">New Technologies Publishing House</publisher-name></publisher></journal-meta><article-meta><article-id pub-id-type="publisher-id">702326</article-id><article-id pub-id-type="doi">10.17587/it.30.579-584</article-id><article-categories><subj-group subj-group-type="toc-heading" xml:lang="en"><subject>Articles</subject></subj-group><subj-group subj-group-type="toc-heading" xml:lang="ru"><subject>Статьи</subject></subj-group><subj-group subj-group-type="article-type"><subject>Conference Report, Theses of Report</subject></subj-group></article-categories><title-group><article-title xml:lang="en">Architecture independent test templates for virtual machines and microprocessors</article-title><trans-title-group xml:lang="ru"><trans-title>Архитектурно независимые тестовые шаблоны для виртуальных машин и микропроцессоров</trans-title></trans-title-group></title-group><contrib-group><contrib contrib-type="author"><name-alternatives><name xml:lang="en"><surname>Protsenko</surname><given-names>A. S.</given-names></name><name xml:lang="ru"><surname>Проценко</surname><given-names>А. С.</given-names></name></name-alternatives><address><country country="RU">Russian Federation</country></address><bio xml:lang="ru"><p>науч. сотр.</p></bio><email>protsenko@ispras.ru</email><xref ref-type="aff" rid="aff1"/></contrib></contrib-group><aff-alternatives id="aff1"><aff><institution xml:lang="en">Ivannikov Institute for System Programming of the Russian Academy of Sciences</institution></aff><aff><institution xml:lang="ru">Институт системного программирования им. В. П. Иванникова РАН</institution></aff></aff-alternatives><pub-date date-type="pub" iso-8601-date="2024-11-15" publication-format="electronic"><day>15</day><month>11</month><year>2024</year></pub-date><volume>30</volume><issue>11</issue><issue-title xml:lang="ru">Информационные технологии</issue-title><fpage>579</fpage><lpage>583</lpage><history><date date-type="received" iso-8601-date="2026-02-07"><day>07</day><month>02</month><year>2026</year></date><date date-type="accepted" iso-8601-date="2026-02-07"><day>07</day><month>02</month><year>2026</year></date></history><permissions><copyright-statement xml:lang="en">Copyright ©; 2024, Informacionnye Tehnologii</copyright-statement><copyright-statement xml:lang="ru">Copyright ©; 2024, Информационные технологии</copyright-statement><copyright-year>2024</copyright-year><copyright-holder xml:lang="en">Informacionnye Tehnologii</copyright-holder><copyright-holder xml:lang="ru">Информационные технологии</copyright-holder></permissions><self-uri xlink:href="https://journals.eco-vector.com/1684-6400/article/view/702326">https://journals.eco-vector.com/1684-6400/article/view/702326</self-uri><abstract xml:lang="en"><p>To ensure the quality of compilers, virtual machines and microprocessors, testing with the use of test programs is applied. Test templates, i.e. parameterized descriptions of test programs, are used to reduce the resources spent on test creation. For verification of test objects with different architectures, test templates testing the same functional properties can be used. A task of describing templates in an architecture-independent form and its customization for a target architecture arises. The paper proposes a method for creating and using architecture independent test templates. The method is as follows. Architecture dependent constructs that are needed to describe a test template are defined. Based on these constructs, an architecture independent test template is created. Then the template is customized to the architecture of the object under test by describing implementations of the architecture dependent constructs. Realizations of the constructs can be described by different sets of architecturally dependent operations, differing both by the type of data used and by the operations used. Different strategies for selecting the implementations to be used, such as full brute force, random selection, and others, can be applied in the test templates. Providing an interface as the architecture dependent constructs allows the use of third-party generators to create the architecturally independent templates. Rewriting the implementations of the constructs allows the test programs to be derived from the given templates for new architectures. This method was successfully applied to check optimizations in a virtual machine compiler.</p></abstract><trans-abstract xml:lang="ru"><p>Для обеспечения качества компиляторов, виртуальных машин, микропроцессоров применяют тестирование с использованием тестовых программ. Тестовые шаблоны, т. е. параметризованные описания тестовых программ, используются для уменьшения затрачиваемых на создание тестов ресурсов. Для верификации тестируемых объектов с разной архитектурой могут применяться тестовые шаблоны, проверяющие одинаковые функциональные свойства. Возникает задача описания шаблона в архитектурно независимой форме и его настройки на целевую архитектуру.</p> <p>Предлагается метод создания и использования архитектурно независимых тестовых шаблонов, который заключается в следующем. Определяются архитектурно зависимые конструкции, необходимые для описания тестового шаблона. На основе этих конструкций создается архитектурно независимый тестовый шаблон. Затем осуществляется настройка шаблона на архитектуру тестируемого объекта путем описания реализаций архитектурно зависимых конструкций. Реализации конструкций могут быть описаны разными наборами архитектурно зависимых операций, отличающихся как типом используемых данных, так и используемыми операциями. В тестовых шаблонах могут быть применены различные стратегии выбора используемых реализаций, такие как полный перебор, случайный выбор и другие.</p> <p>Предоставление интерфейса в виде архитектурно зависимых конструкций позволяет использовать сторонние генераторы для создания архитектурно независимых шаблонов. Описание архитектурно зависимых конструкций с помощью определенных систем команд позволяет получать тестовые программы по заданным шаблонам для соответствующих архитектур. Данный метод был успешно применен для проверки корректности оптимизирующих преобразований в компиляторе виртуальной машины.</p></trans-abstract><kwd-group xml:lang="en"><kwd>test templates</kwd><kwd>testing</kwd><kwd>instruction set architecture</kwd><kwd>virtual machines</kwd><kwd>test program generator</kwd></kwd-group><kwd-group xml:lang="ru"><kwd>тестовые шаблоны</kwd><kwd>тестирование</kwd><kwd>система команд</kwd><kwd>виртуальные машины</kwd><kwd>генераторы тестовых программ</kwd></kwd-group><funding-group/></article-meta></front><body></body><back><ref-list><ref id="B1"><label>1.</label><citation-alternatives><mixed-citation xml:lang="en">Behm M., Ludden J., Lichtenstein Y., Rimon M., Vinov M. Industrial experience with test generation languages for processor verification, Proceedings of the 41th Design Automation Conference, DAC, 2004, pp. 36—40.</mixed-citation><mixed-citation xml:lang="ru">Behm M., Ludden J., Lichtenstein Y., Rimon M., Vinov M. Industrial experience with test generation languages for processor verification // Proceedings of the 41th Design Automation Conference, DAC. 2004. P. 36—40.</mixed-citation></citation-alternatives></ref><ref id="B2"><label>2.</label><citation-alternatives><mixed-citation xml:lang="en">Tatarnikov A. D. Combinatorial Test Program Generation for Microprocessors Based on Formal Specifications of Instruction Set Architecture, Problemy razrabotki perspektivnyh mikro- i nanoelektronnyh sistem (MES), 2016, no. 2, pp. 38—45.</mixed-citation><mixed-citation xml:lang="ru">Татарников А. Д. Комбинаторная генерация тестовых программ для микропроцессоров на основе формальных спецификаций системы команд // Проблемы разработки перспективных микро- и наноэлектронных систем (МЭС). 2016. № 2. С. 38—45.</mixed-citation></citation-alternatives></ref><ref id="B3"><label>3.</label><citation-alternatives><mixed-citation xml:lang="en">Stocks P., Carrington D. A. Test templates: a specification-based testing framework, Proceedings — International Conference on Software Engineering, 1993, pp. 405—414, doi: 10.1109/ ICSE.1993.346025.</mixed-citation><mixed-citation xml:lang="ru">Stocks P., Carrington D. A. Test templates: a specification-based testing framework // Proceedings — International Conference on Software Engineering. 1993. P. 405—414. DOI: 10.1109/ICSE.1993.346025. 1. Behm M., Ludden J., Lichtenstein Y., Rimon M., Vinov M. Industrial experience with test generation languages for processor verification // Proceedings of the 41th Design</mixed-citation></citation-alternatives></ref><ref id="B4"><label>4.</label><citation-alternatives><mixed-citation xml:lang="en">Zang Zh., Wiatrek N., Gligoric M., Shi A. Compiler Testing using Template Java Programs, Proceedings of the 37th IEEE/ ACM International Conference on Automated Software Engineering, ASE, 2022.</mixed-citation><mixed-citation xml:lang="ru">Zang Zh., Wiatrek N., Gligoric M., Shi A. Compiler Testing using Template Java Programs //Proceedings of the 37th IEEE/ACM International Conference on Automated Software Engineering, ASE. 2022.</mixed-citation></citation-alternatives></ref><ref id="B5"><label>5.</label><citation-alternatives><mixed-citation xml:lang="en">Kamkin A. S. Generation of test programs for microprocessors (in Russian), Trudy ISP RAN, 2008, vol. 14, no. 2, pp. 23—64.</mixed-citation><mixed-citation xml:lang="ru">Камкин А. С. Генерация тестовых программ для микропроцессоров // Труды ИСП РАН. 2008. Т. 14, № 2. С. 23—64.</mixed-citation></citation-alternatives></ref><ref id="B6"><label>6.</label><citation-alternatives><mixed-citation xml:lang="en">Adir A., Almog E., Fournier L., Marcus E., Rimon M., Vinov M., Ziv A. Genesys-Pro: Innovations in Test Program Generation for Functional Processor Verification, IEEE Design &amp; Test of Computers, 2004, vol. 21, no. 2, pp. 84—93.</mixed-citation><mixed-citation xml:lang="ru">Adir A., Almog E., Fournier L., Marcus E., Rimon M., Vinov M., Ziv A. Genesys-Pro: Innovations in Test Program Generation for Functional Processor Verification // IEEE Design &amp; Test of Computers. 2004. Vol. 21, N. 2. P. 84—93.</mixed-citation></citation-alternatives></ref><ref id="B7"><label>7.</label><citation-alternatives><mixed-citation xml:lang="en">Mahapatra R. N., Bhojwani P., Lee J., Kim Y. Microprocessor Evaluations for Safety-Critical, Real-Time Applications: Authority for Expenditure. Phase 3 Report. NTIS, Springfield, Virginia 22161, 2009, no. 43. 43 p.</mixed-citation><mixed-citation xml:lang="ru">Mahapatra R. N., Bhojwani P., Lee J., Kim Y. Microprocessor Evaluations for Safety-Critical, Real-Time Applications: Authority for Expenditure. Phase 3 Report. NTIS, Springfield, Virginia 22161. 2009. N. 43. 43 p.</mixed-citation></citation-alternatives></ref><ref id="B8"><label>8.</label><citation-alternatives><mixed-citation xml:lang="en">Archive of presentation slides "Introducing Obsidian Software and RAVEN-GCS for PowerPC" [Online], available at: https://www.slideshare.net/DVClub/introducing-obsidian-software-and-ravengcs-for-powerpc.</mixed-citation><mixed-citation xml:lang="ru">Архив слайдов презентации "Introducing Obsidian Software and RAVEN-GCS for PowerPC". URL: https://www. slideshare.net/DVClub/introducing-obsidian-software-andravengcs-for-powerpc.</mixed-citation></citation-alternatives></ref><ref id="B9"><label>9.</label><citation-alternatives><mixed-citation xml:lang="en">Gribkov I. V., Zakharov A. V., Koltsov P. P. et al. Development of the INTEG microprocessor stochastic testing system, Programmnyye produkty i sistemy, 2010, no. 2, pp. 14—23 (in Russian).</mixed-citation><mixed-citation xml:lang="ru">Грибков И. В., Захаров А. В., Кольцов П. П. и др. Развитие системы стохастического тестирования микропроцессоров INTEG // Программные продукты и системы. 2010. № 2. С. 14—23.</mixed-citation></citation-alternatives></ref><ref id="B10"><label>10.</label><citation-alternatives><mixed-citation xml:lang="en">Tatarnikov A. D. Language for Describing Templates for Test Program Generation for Microprocessors, Proceedings of the Institute for System Programming of the RAS (Proceedings of ISP RAS), 2016, vol. 28, no. 4, pp. 77—98, doi: 10.15514/ISPRAS-2016-28(4)-5.</mixed-citation><mixed-citation xml:lang="ru">10.1109/ICSE.1993.346025.</mixed-citation></citation-alternatives></ref><ref id="B11"><label>11.</label><citation-alternatives><mixed-citation xml:lang="en">Ruby language [Online], available at: http://www.rubylang.org.</mixed-citation><mixed-citation xml:lang="ru">Язык Ruby. URL: http://www.ruby-lang.org.</mixed-citation></citation-alternatives></ref><ref id="B12"><label>12.</label><citation-alternatives><mixed-citation xml:lang="en">Seonghun J., Youngchul Cho, Daeyong S., Changyeon J., Yenjo H., Soojung R., Jeongwook K., Bernhard E. Random Test Program Generation for Reconfigurable Architectures, 13th International Workshop on Microprocessor Test and Verification (MTV), 2012, 6 p.</mixed-citation><mixed-citation xml:lang="ru">Seonghun J., Youngchul Cho, Daeyong S., Changyeon J., Yenjo H., Soojung R., Jeongwook K., Bernhard E. Random Test Program Generation for Reconfigurable Architectures // 13th International Workshop on Microprocessor Test and Verification (MTV). 2012. 6 p.</mixed-citation></citation-alternatives></ref><ref id="B13"><label>13.</label><citation-alternatives><mixed-citation xml:lang="en">Egger B., Song E., Lee H., Shin D. Random Test Program Generation for Verification and Validation of the Samsung Reconfigurable Processor, Journal of Systems Architecture, 2019, vol. 97, doi: 10.1016/j.sysarc.2019.05.007.</mixed-citation><mixed-citation xml:lang="ru">Egger B., Song E., Lee H., Shin D. Random Test Program Generation for Verification and Validation of the Samsung Reconfigurable Processor // Journal of Systems Architecture. 2019. Vol. 97. DOI: 10.1016/j.sysarc.2019.05.007.</mixed-citation></citation-alternatives></ref><ref id="B14"><label>14.</label><citation-alternatives><mixed-citation xml:lang="en">Chen J., Wang G., Hao D., Xiong Y., Zhang H., Zhang L. History-Guided Configuration Diversification for Compiler TestProgram Generation, 2019 34th IEEE/ACM International Conference on Automated Software Engineering (ASE), San Diego, CA, USA, 2019, pp. 305—316, doi: 10.1109/ASE.2019.00037.</mixed-citation><mixed-citation xml:lang="ru">Chen J., Wang G., Hao D., Xiong Y., Zhang H., Zhang L. History-Guided Configuration Diversification for Compiler TestProgram Generation // 2019 34th IEEE/ACM International Conference on Automated Software Engineering (ASE). San Diego, CA, USA. 2019. P. 305—316. DOI: 10.1109/ASE.2019.00037.</mixed-citation></citation-alternatives></ref><ref id="B15"><label>15.</label><citation-alternatives><mixed-citation xml:lang="en">Rabin Md R. I., Alipour M. Configuring Test Generators Using Bug Reports: A Case Study of GCC Compiler and Csmith, The 36th ACM/SIGAPP Symposium on Applied Computing, SAC, 2021, pp. 1750—1758, doi: 10.1145/3412841.3442047.</mixed-citation><mixed-citation xml:lang="ru">Rabin Md R. I., Alipour M. Configuring Test Generators Using Bug Reports: A Case Study of GCC Compiler and Csmith // The 36th ACM/SIGAPP Symposium on Applied Computing, SAC. 2021. P. 1750—1758. DOI: 10.1145/3412841.3442047.</mixed-citation></citation-alternatives></ref><ref id="B16"><label>16.</label><citation-alternatives><mixed-citation xml:lang="en">Loop-Invariant Code Motion (LICM) [Online], available at: https://en.wikipedia.org/wiki/Loop-invariant_code_motion.</mixed-citation><mixed-citation xml:lang="ru">Loop-Invariant Code Motion (LICM). URL: https:// en.wikipedia.org/wiki/Loop-invariant_code_motion.</mixed-citation></citation-alternatives></ref><ref id="B17"><label>17.</label><citation-alternatives><mixed-citation xml:lang="en">Zelenov S. V., Zelenova S. A. Model-Based Testing of Optimizing Compilers, TestCom/FATES 2007, LNCCN, vol. 4581, pp. 365—377.</mixed-citation><mixed-citation xml:lang="ru">Zelenov S. V., Zelenova S. A. Model-Based Testing of Optimizing Compilers // TestCom/FATES. 2007. LNCCN. Vol. 4581. P. 365—377.</mixed-citation></citation-alternatives></ref><ref id="B18"><label>18.</label><citation-alternatives><mixed-citation xml:lang="en">MicroTESK test program generator [Online], available at: https://forge.ispras.ru/projects/microtesk.</mixed-citation><mixed-citation xml:lang="ru">Генератор тестовых программ MicroTESK. URL: https://forge.ispras.ru/projects/microtesk.</mixed-citation></citation-alternatives></ref></ref-list></back></article>
