A hybrid approach for accelerating detailed routing of very large-scale integration (VLSI) circuits is proposed. The method combines a neural network model based on the U-Net architecture enhanced with Self-Attention and the classical Rip-Up and Reroute (R&R) algorithm. Experimental results demonstrate a significant acceleration of the routing process without loss of quality. The proposed solution illustrates the practical efficiency of machine learning methods in the field of physical design automation. The proposed approach represents the detailed routing task in a tensor form that preserves complete spatial information required for constructing routing paths. А modified deep learning segmentation model is developed to predict routing patterns for multiple nets simultaneously within a shared topological region. The predictions of the neural network serve as an initial approximation for the heuristic R&R algorithm, which substantially reduces the number of iterations needed to reach convergence. The neural network is trained on data derived from the results of global routing and physical design parameters extracted from LEF/DEF and Guide files. А new data decomposition method is introduced that allows the neural model to be adapted to any process design kit (PDK) by partitioning the routing layers into independent stacks. Tests on real integrated circuits show that the proposed method achieves up to a fivefold speedup compared to the open-source router OpenLane, particularly for large-scale designs. The study highlights the potential of deep learning in reducing the computational cost of detailed routing, one of the most time-consuming stages in VLSI physical synthesis. The approach demonstrates scalability, adaptability to different design rules, and opportunities for further performance gains through model optimization and integration into existing EDA workflows.