Example of implementation of a single-CYCLE RISC-V processor core using Altera Quartus II Cad

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Abstract

One of the areas of work in the field of creating projects based on the RISC-V architecture is the development of prototypes of processors on the FPGA platform. The article considers an example of the implementation of a single-cycle RISC-V processor core on the Cyclone V FPGA basis using the Altera Quartus II CAD system.

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About the authors

A. V. Strogonov

Воронежский государственный технический университет

Author for correspondence.
Email: andreistrogonov@mail.ru

доктор технических наук, профессор кафедры твердотельной электроники

Russian Federation, 394006, Воронеж

A. Vinokurov

Воронежский государственный технический университет

Email: andreistrogonov@mail.ru
Russian Federation, 394006, Воронеж

A. I. Strogonov

Воронежский государственный университет

Email: andreistrogonov@mail.ru

факультет компьютерных наук, кафедра программирования и информационных технологий, ассистент

Russian Federation, Воронеж

References

  1. Строгонов А.В., Бордюжа О.Л., Строгонов А.И. Эффективный подход в разработке управляющих автоматов микропроцессорных ядер // ЭЛЕКТРОНИКА: Наука, Технология, Бизнес. 2024. № 1. С. 78–86.
  2. Харрис С.Л., Харрис Д. Цифровая схемотехника и архитектура компьютера RISC-V / Пер. с англ. В.С. Яценкова, А.Ю. Романова; под ред. А.Ю. Романова. М.: ДМК Пресс, 2021. 810 с.
  3. Harris S.L., Harris D. Digital Design and Computer Architecture RISC-V Edition. 2022. ISBN: 978-0-12-820064-3.
  4. Intel Quartus Prime Pro Edition User Guide. Design Recommendations. UG-20131. ID: 683082. Version: 2021.10.04.
  5. XST User Guide. 10.1. ROMs Using Block RAM Resources HDL Coding Techniques // www.xilinx.com.
  6. https://pastebin.com/ew0SACWy.
  7. https://luplab.gitlab.io/rvcodecjs/#q=00C00193&abi=false& isa=AUTO.

Supplementary files

Supplementary Files
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1. JATS XML
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2. Fig. 1. Structural diagram of a single-cycle RISC-V processor core

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3. Fig. 2. Functional diagram of a single-cycle RISC-V processor core

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4. Fig. 3. Assembler and machine codes (far right column – ROM firmware, text file riscvtest.txt)

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5. Fig. 4. The top level of the hierarchy of a single-cycle RISC-V processor core in the Quartus II CAD system

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6. Fig. 5. Data path of a single-cycle RISC-V processor core in Quartus II CAD system

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7. Fig. 6. Error compiling the VHDL code of the ROM from example 7.14 of [1]

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8. Fig. 7. Example 1: VHDL code for a ROM that compiles without errors in Quartus II, but generates an “empty” mif file.

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9. Fig. 8. Example 2: fragment of generated “empty” mif-file from VHDL-code of ROM

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10. Fig. 9. Example 3: fragment of generated mif file from SystemVerilog ROM code

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11. Fig. 10. RTL representation from SystemVerilog ROM code

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12. Fig. 11. Example 4: ROM initialization directly from HDL code

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13. Fig. 12. RTL representation from VHDL code of ROM (Example 4)

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14. Fig. 13. Example 5: fragment of the generated mif file when initializing the ROM directly in the HDL code

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15. Fig. 14. Example 6: fragment of VHDL code of data RAM (example 7.15, works [1, 2])

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16. Fig. 15. Example 7: VHDL code fragment of data RAM with one process operator for writing and reading

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17. Fig. 16. Example 8: ALU code with SLT instruction support

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18. Fig. 17. Time diagram of successful completion of the test shown in Fig. 3

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19. Fig. 18. Window of the online program "RISC-V Command Encoder/Decoder", which allows you to translate machine code into assembler code with the selection of command fields in binary code

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Copyright (c) 2024 Strogonov A.V., Vinokurov A., Strogonov A.I.