HARDWARE IMPLEMENTATION OF THE UNIT OF THE GNSS CONSUMER

Толық мәтін

Introduction. The development of the hardware ar- chitecture of the digital processing of GLONASS/GPS signals is one of the priority directions of development of consumer navigation equipment. The computational costs of the implementation of algorithms for processing navi- gation signals as a result affect the cost of the device and also determine the future path of hardware development. The processing of navigation signals at the intermedi- ate frequency requires increased hardware costs due to the fact that computing units operating at frequencies above 100 MHz requires pipelining calculations, and the com- bined use of computational algorithms. After dropping the navigation signal processing frequency it is possible to reduce hardware costs through the use of a suitable architecture. Adders architectures overview. Any synthesized computational algorithm, which can be described in hardware description languages such as VHDL and Verilog, consists of the sum and shift register operations. There are several major architectures of adders, each of which has the benefit of either the speed or ease of implementation [1-5]. The simplest architecture is the architecture of the ad- der, based on sequential bitmap summation of binary numbers and carry bit propagation from the least signifi- cant bit (LSB) to the most significant bit (MSB). The In this architecture the speed of calculations depends on the length and composition of the terms of the bit se- quence and depends on the length of the carry bit pre-calculation unit. For this architecture it has a value of a parameter logic circuits like fan-in. It is the number of inputs that can be connected to a circuit. Another effective adder architecture is based on the simultaneous preliminary carry bit calculation to MSB bits for the group at Cin = 0 and Cin = 1, and then selecting the active unit based on the calculated value of Сin. In contrast to the architecture of a preliminary carry bit calculation to MSB, in this architecture, the calculation of transfer is possible to perform consistently in the elements of full adders. In this case, the sum bit sequences are pos- sible in areas to which the input value of the carry bit has not reached yet. Thus it is possible to reduce the bit sequences calculation time in multiplies of the length of the selected transfer to MSB calculation interval. There are combinations of bits in the bit string of terms that lead to the propagation of carry bit just for a group of bits. In this case, the calculation of carry bit transfer to MSB bit may be skipped [10; 11]. Then the sum of bit sequences in a limited range is calculated according to (2). ì pi = Xi Yi + XiYi , ï p p ... p = 1, basic computational element of this architecture is called a full adder (FA). Despite its simplicity, the main draw- Si,i+n ï i+n i+n-1 = í ï 0, Cin,i i = 0, (2) back of this architecture is a linear dependence of the delay calculation on the amount of bit terms, as at each iteration of addition it is necessary to consider the carry bit propagation [6-8]. Another, the most demanded, architecture differs in that the propagation of carry bit is pre-calculated accord- ing to the so-called scheme of Manchester [9; 10]. The concepts of carry generation and carry transition are introduced in this architecture. Preliminary calculation (1) is carried out once for a group of bits. It reduces the amount of calculations for the following group of bits proportionally: gi = XiYi , pi = Xi Yi + XiYi , Ci+1 = gi + piCin,i , (1) Ci+2 = gi+1 + pi+1g i + pi+1 piCin,i , Ci+ n = gi+ n-1 + ... + pi+ n-1... pi+1gi + pi+n-1... piCin,i . îï 1, Cin,i = 1. For this architecture such factors as the probability of the emergence of groups of bits, that create transportation of the carry bit, are of great importance (fig. 1). Usually, the best result is obtained by sharing multiple architectures. At the same time, organizing a pipelined calculation [10; 11], for such an option another important element of computing is introduced as a carry-save adder (CSA). This adder is based on the fact that the transfer to MSB is passed to the next iteration of the pipeline, that allows avoiding the transference computation in the cur- rent iteration, and allows you to work in parallel adder. High throughput hardware design. There are several ways to improve the effectiveness of the described archi- tectures (fig. 1). For the carry-lookahead adder one must use logic with a large fan-in. For the carry-select adder, ripple-carry adder and carry-skip adder one may itera- tively use one and the same group of adders for different groups of bit sequences included in the terms [10; 11]. Fig. 1. The options of improving the efficiency of the architectures of adders Рис. 1. Варианты повышения эффективности архитектур сумматоров Hardware processing units operating at frequencies below 10 MHz are greatly simplified due to the choice of architecture adders, using the capabilities of FPGA chip more effectively. In the development of computer architectures, operat- ing at frequencies 100-200 MHz, pipelining calculations are necessary (fig. 2). Despite the fact that the pipelined architecture has a large overhead for alignment of delay of computing unit, its use is justified in such tasks as: 1) the encoding / decoding signals in real time; 2) decrease / increase in operating frequency of the signal; 3) the processing of wideband signals. To build consumer navigation equipment GLONASS / GPS the following building blocks of digital processing are needed: 1) the scheme of frequency conversion; 2) the correlator of pseudo-random sequence; 3) the signal tracking scheme. Frequency conversion scheme is realized based on the pipelined adder and pipelined multiplier (fig. 3). Pipelined multiplier is capable of operating at a frequency of > 100 MHz and perform calculations for 1 clock cycle. Also in the GLONASS / GPS navigation consumer device the multiplier is used for the correlation processing of a navigation signal at the intermediate frequency. After down-frequency conversion the navigation signal may use frequency multipliers operating at frequencies less than 10 MHz (fig. 4). For such processing frequency extra hardware optimization and the use of asynchronous adders to construct a pipelined multipliers are possible (fig. 4). In addition, modern FPGA chips have a large number of DSP layers that can also be used to implement computational units. For example, the implementation of complex pipelined multiplier operating at a frequency of 100 MHz takes 25-30 thousands triggers. At the same time in current FPGA chips it will take only 3 DSP hard- ware layers.To build consumer navigation equipment GLONASS / GPS the following building blocks of digital processing are needed: 1) the scheme of frequency conversion; 2) the correlator of pseudo-random sequence; 3) the signal tracking scheme. Fig. 2. Conveyor adder with preliminary transfer calculation Рис. 2. Конвейерный сумматор с предварительным расчётом переноса Рис. 3. Конвейерный умножитель Another important element of the GLONASS / GPS navigation consumer equipment is a digital generator of lettered frequencies (LFG). This oscillator is used to down-convert the carrier frequency of the navigation signal [12; 13]. The LFG can be implemented in two ways. In the first method LFG can be made based on parallel Flash- memory. This method is simple to implement and requires preservation of samples prior workers lettered frequencies. Among the shortcomings of this method one can distinguish that one frequency channel with a sam- pling frequency of 100-200 MHz requires one external chip Flash-memory. Also, with such a realization it is possible only operate at fixed frequencies with samples previously saved to Flash-memory. Another method is based on the CORDIC processor operating in rotation mode (fig. 5). Pipelined CORDIC processor is identical to pipelined multiplier by hardware resources, at the same time it allows you to get just two harmonic components of SIN and COS signal [14; 15]. CORDIC processor operates according to the expressions: x(i+1) = x(i) - di y(i) 2-i , where x = cos (z), y = sin (z), z - target angle, dÎ {-1, 1}. To accelerate the computation intermediate values tan-12-i are calculated beforehand and stored in registers. At each iteration, the intermediate value of angle is checked, then angle increment is selected in the next iteration of the pipeline. Because this algorithm implements the pseudo-rotation, the length of the vector after the rotation is increased by a factor of K = 1.64676. To compensate for this effect, the initial length of the vector is chosen to be 1 / K = 0.60725. Pipelined implementation allows to calculate the value of sin (z) and cos (z) in a single cycle, and it is capable of operating at a frequency of more than 100 MHz. The advantages of implementing LFG on CORDIC processor may include the possibility of dynamic reconfiguration of the operating frequency of the measuring path, providing performance for GLONASS / GPS signals in L1 or L2 bands. Also there is the ability to configure the LFG initial phase for hardware alignment signals paths. The disadvantage of this method is the high cost of hardware implementation, since there is a need to perform pipelin- ing calculations at the block operating frequencies of 100-200 MHz. To implement this block not more than y(i+1) = y(i) + dix(i) 2-i , (3) 10 DSP layer in FPGA are used, which can significantly z(i+1) = z(i) - di tan-1 2-i , reduce hardware costs. Fig. 4. Asynchronous conveyor multiplier Рис. 4. Асинхронный конвейерный умножитель Рис. 5. Конвейерный CORDIC процессор (режим вращения) Conclusion. The hardware architectures of computa- tional units reviewed above have the property of deter- minism. This feature is of great importance in the con- struction of navigation consumer equipment GLONASS / GPS, because they allow taking into account the delay in the path of digital signal processing at the design stage. Despite the high price of pipelined performance of com- puting units, it makes possible to handle the navigation signals at a sampling frequency of 200 MHz. As the high sampling rate allows keeping the form of the navigation signal, it will eventually allow high-precision measure- ments of the phase of navigation signal. Collectively, the development of computing architectures will allow seeing the weaknesses of a computing device and make better use of the potential of modern FPGA devices.

Авторлар туралы

A. Sokolovskiy

Siberian Federal University

79, Svobodny Av., Krasnoyarsk, 660041, Russian Federation

E. Veisov

Siberian Federal University

79, Svobodny Av., Krasnoyarsk, 660041, Russian Federation

V. Ratushniak

Siberian Federal University

Email: oborona-81@ya.ru
79, Svobodny Av., Krasnoyarsk, 660041, Russian Federation

D. Rizhkov

JSC “Academician M. F. Reshetnev” Information Satellite Systems”

52, Lenin Str., Zheleznogorsk, Krasnoyarsk region, 662972, Russian Federation

S. Vysotsky

JSC “Academician M. F. Reshetnev” Information Satellite Systems”

52, Lenin Str., Zheleznogorsk, Krasnoyarsk region, 662972, Russian Federation

Әдебиет тізімі

Қосымша файлдар