Email this article Simulation of Si–sio2 interface depassivation in LDMOS transistor structure using Sentaurus TCAD
- Authors: Alekseev R.1, Maltsev V.1
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Affiliations:
- АО «НИИЭТ»
- Issue: No 2 (2025)
- Pages: 116-120
- Section: Reliability and validation
- URL: https://journals.eco-vector.com/1992-4178/article/view/680355
- DOI: https://doi.org/10.22184/1992-4178.2025.243.2.116.120
- ID: 680355
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Abstract
The article discusses methods for predicting the degradation processes of LDMOS transistors during operation under various temperature conditions. Simulation of an LDMOS transistor in Sentaurus TCAD showed that changing temperature conditions
leads to different rates of degradation of transistor characteristics, such as threshold voltage and leakage current.
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About the authors
R. Alekseev
АО «НИИЭТ»
Author for correspondence.
Email: redactor@electronics.ru
ведущий инженер
Russian FederationV. Maltsev
АО «НИИЭТ»
Email: redactor@electronics.ru
инженер-технолог 3 категории
Russian FederationReferences
- Manzoor S., Karim M., Soin N. Analyzing p-MOSFET Lifetime by Employing R-D Model & MOS Device Theory // Applied Mechanics And Materials. 2012. Vol. 229–231. PP. 1626–1629.
- Davis E.A. Hydrogen in silicon // Journal of Non-Crystalline Solids. 1996. Vol. 198–200. PP. 1–10.
- Cartier E., Stathis J.H., Buchanan D.A. Passivation and depassivation of silicon dangling bonds at the Si/SiO2 interface by atomic hydrogen // Applied Physics Letters. 1993. Vol. 63. PP. 1510–1512.
- Zhongming S., Mieville J.-P., Dutoit M. Random Telegraph signals in deep submicrons n-MOSFET’s // IEEE Transactions On Electron Devices. 1994. Vol. 41. №7. PP. 1161–1168.
- Haggag A., McMahon W., Hess K., Cheng K., Lee J., Lyding J. High-Performance Chip Reliability from Short-Time-Tests Statastacal Models for Optacal Interconnect and HCI/TDDB/NBTI Deep-Submicron Transistor Failures // IEEE International Reliability Physics Symposium Proceedings. 2001. PP. 271–279.
- Chen G., Li M.F., Ang C.H., Zheng J.Z., Kwong D.L. Dynamic NBTI of p-MOS Transistors and Its Impact on MOSFET Scaling // IEEE Electron Device Letters. 2002. Vol. 23. № 12. PP. 734–736.
- Doyle B.S., Mistry K.R., Jackson D.B. Examination of Gradual-Junction p-MOS Structures for Hot Carrier Control Using a New Lifetime Extraction Method // IEEE Transactions On Electron Devices. 1992. Vol. 39 № 10. PP. 2290–2297.
- Daniel M. Evolution of Total Ionizing Dose Effects in MOS Devices with Moore’s Law Scaling // I EEE Transactions on Nuclear Science. 2017. Vol. 65. №8. PP. 1465–1481.
- Токмолдин С.Ж. Пассивация атомарным водородом дефектов в кристаллическом кремнии: автореф. дис. д-ра физ.-мат. наук: 01.04.07 // Физико-технический институт Министерства науки Академии наук Республики Казахстан. Алматы, 1998. 37 с.
- Строгонов А., Белых М., Пермяков Д., Полковников В. Методы проектирования БИС с учетом надежности // ЭЛЕКТРОНИКА: Наука, Технология, Бизнес. 2021. №3. С. 46–56.
- Pfäffli P., Tikhomirov P., Xu X., Avci I., Oh Y.-S., Balasingam P., Krishnamoorthy S., Ma T. TCAD for reliability // Microelectronics Reliability. 2012. Vol. 52. PP. 1761–1768.
- Pfäffli P., Wong H.Y., Xu X., Silvestri L., Lin X.W., Yang T., Tiwari R., Mahapatra S., Motzny S., Moroz V., Ma T. TCAD modeling for reliability // Microelectronics Reliability. 2018. Vol. 88–90. PP. 1083–1089.
- Алексеев Р.П., Семейкин И.В., Цоцорин А.Н., Куршев П.Л. LDMOS: новые разработки АО «НИИЭТ» // ЭЛЕКТРОНИКА: Наука, Технология, Бизнес. 2023. №2. С. 92–96.
- Mahapatra S., Kumar P.B. On the Generation and Recovery of Interface Traps in mosfets Subjected to NBTI, FN, and HCI Stress // IEEE Transactions On Electron Devices. 2006. Vol. 5. № 7. PP. 1583–1592.
Supplementary files
Supplementary Files
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JATS XML
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Fig. 1. Fragment of the LDMOS transistor structure model, designed using Process
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Fig. 2. Transient response before and after 720 hours of testing
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Fig. 3. Fragment of the transition characteristic before the tests and after 1, 4, 8, 24 and 720 hours of testing
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Fig. 4. Dependence of the concentration of interband traps at the boundary of the gate dielectric on the test time
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Fig. 5. Dependence of the concentration of interface traps on the test time and temperature
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Fig. 6. Dependence of the transition characteristic on temperature
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