Email this article Oxide layer etch-back optimization during TSV formation
- Authors: Sukhanov D.1
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Affiliations:
- ООО «Остек-ЭК»
- Issue: No 9 (2025)
- Pages: 98-102
- Section: Micro and nanostructures
- URL: https://journals.eco-vector.com/1992-4178/article/view/697582
- DOI: https://doi.org/10.22184/1992-4178.2025.251.9.98.102
- ID: 697582
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Abstract
The article presents an overview of methods for optimizing the oxide layer etching process during the Through-Silicon-Via (TSV) formation. It further analyzes their impact on the quality and reliability of 3D integrated circuits.
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About the authors
D. Sukhanov
ООО «Остек-ЭК»
Author for correspondence.
Email: micro@ostec-group.ru
заместитель технического директора
Russian Federation, 121467, г. Москва, ул. Молдавская, д. 5, стр. 2References
- Bhesetti S. S., Chandra R., Hemanth K. C., Darshini S. TSV oxide etch-back optimization for the via-last integration scheme // Chip Scale Review. May-June, 2023. PP. 15–20.
Supplementary files
Supplementary Files
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JATS XML
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Fig. 1. Scheme of formation of an oxide insulator for the via-last integration approach (a); the oxide layer of the upper corner of TSV after the oxide etching process (b)
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Fig. 2. The scheme of the technological process
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Fig. 3. TSV structure before applying the oxide coating
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Fig. 4. TSV structure after deposition of the oxide insulating layer
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Fig. 5. A model for determining the conditions that ensure a higher rate of oxide etching at the TSV bottom and a lower rate in the upper corner.
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Fig. 6. Passivation layer deposition in the upper corner of TSV
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7. An unoptimized process led to a higher rate of oxide etching in the upper corner than at the TSV bottom.
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Figure 8. The optimized process led to an increase in ER at the bottom of TSV and a decrease in ER in the upper corner
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