Development of domestic software tools for physical design and digital VLSI verification

Мұқаба

Дәйексөз келтіру

Толық мәтін

Ашық рұқсат Ашық рұқсат
Рұқсат жабық Рұқсат берілді
Рұқсат жабық Рұқсат ақылы немесе тек жазылушылар үшін

Аннотация

Lomonosov Moscow State University, as part of a cooperation headed by ISTC MIET, is developing three components of VLSI CAD: physical synthesis tool, parasitic parameters calculation tool and universal database for storing information on the IC being developed. The article discusses the tasks solved in the course of this work.

Толық мәтін

Рұқсат жабық

Авторлар туралы

V. Sazonov

МГУ имени М.В. Ломоносова

Хат алмасуға жауапты Автор.
Email: sazonov@cosmos.msu.ru

декан факультета космических исследований, д.ф.-м.н.

Ресей

R. Erokhin

МГУ имени М.В. Ломоносова

Email: sazonov@cosmos.msu.ru

факультет космических исследований, научный сотрудник

Ресей

V. Serov

МГУ имени М.В. Ломоносова

Email: sazonov@cosmos.msu.ru

факультет космических исследований, старший программист

Ресей

M. Sheblaev

МГУ имени М.В. Ломоносова

Email: sazonov@cosmos.msu.ru

факультет космических исследований, ассистент

Ресей

Әдебиет тізімі

  1. LEF/DEF 5.8 Language Reference // https://coriolis.lip6.fr/doc/lefdef/lefdefref/lefdefref.pdf.
  2. GDSII Stream Format Manual // http://bitsavers.informatik.uni-stuttgart.de/pdf/calma/GDS_II_Stream_Format_Manual_6.0_Feb87.pdf.
  3. Horowitz M., Dutton. R.W. Resistance Extraction from Mask Layout Data // IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, V. 2, No. 3, PP. 145–150, July 1983.
  4. Kao W.H., Lo C-Y., Basel M., Singh R. Parasitic extraction: current state of the art and future trends // Proceedings of the IEEE, V. 89, No. 5, PP. 729–739, May 2001.
  5. Тихонов А.Н., Самарский А.А. Уравнения математической физики. Учеб. пособие для вузов. М.: Наука, 1977. 735 с.
  6. Cao W., Harrington R., Mantz J., Sarkar T. Multiconductor transmission lines in multilayered dielectric media // IEEE Trans. Microwave Theory Tech., V. MTT-32, PP. 439–450, Apr. 1984.
  7. Arora N.D., Roal K.V., Schumann R., Richardson L.M. Modeling and extraction of interconnect capacitances for multi-layer VLSI circuits // IEEE Trans. Computer-Aided Design, V. 15, PP. 58–67, Jan. 1996.
  8. Препарата Ф., Шеймос М. Вычислительная геометрия: Введение: Пер. с англ. М.: Мир, 1989. 478 с.
  9. Lopez A. How is the Design Process of Microchips: Analog IC Design Flow to Tapeout // https://miscircuitos.com/design-process-of-chips-asics-flow-from-design-totapeout/.
  10. Virtuoso Studio Custom design for the real world // www.cadence.com.
  11. Analog Design // www.synopsys.com.
  12. IC Design, Verification & Manufacturing Products // https://eda.sw.siemens.com/en-US/ic/products/.
  13. Bailey B. 10X productivity boost is nothing to be sneezed // www.eetimes.com.
  14. Bailey B. A look back on 2012: Design tools and flows // www.eetimes.com.
  15. Wang Q. Opinion: What Comes After Power Intent Formats? // www.eetimes.com.
  16. Lavagno L. et al. Electronic design automation for IC system design, verification, and testing // CRC Press. 2017.
  17. Burstein M., Youssef M.N. Timing influenced layout design // 22nd ACM/IEEE Design Automation Conference. IEEE, 1985. PP. 124–130.
  18. Alpert C.J., Mehta D.P., Sapatnekar S.S. Handbook of algorithms for physical design automation // CRC press, 2008.
  19. Boyd S.P., Vandenberghe L. Convex optimization // Cambridge university press, 2004.
  20. Kahng A.B. et al. VLSI physical design: from graph partitioning to timing closure // Netherlands: Springer, 2011. V. 312.
  21. Sherwani N.A. Algorithms for VLSI physical design automation // Springer Science & Business Media. 2012.
  22. Кристофидес Н. Теория графов. Алгоритмический подход. 1978.
  23. Flach G. et al. An incremental timing-driven flow using quadratic formulation for detailed placement // 2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC). IEEE. 2015. PP. 1–6.
  24. Kim M.C. et al. A SimPLR method for routability-driven placement // 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD). IEEE. 2011. PP. 67–73.
  25. Brenner U., Struzyna M., Vygen J. BonnPlace: Placement of leading-edge chips by advanced combinatorial algorithms // IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2008. V. 27. No. 9. PP. 1607–1620.
  26. Borkar S. Design perspectives on 22 nm CMOS and beyond // Proceedings of the 46th Annual Design Automation Conference. 2009. PP. 93–94.
  27. Tsay R.S. An exact zero-skew clock routing algorithm // IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 1993. V. 12. No. 2. PP. 242–249.

Қосымша файлдар

Қосымша файлдар
Әрекет
1. JATS XML
Жүктеу
2. Fig. 1. Cell placement using the analytical method [16]

Жүктеу (64KB)
Метадеректер
3. Fig. 2. Legalization of cells [16]

Жүктеу (40KB)
Метадеректер
4. Fig. 3. Applying the rip-up-and-re-route methodology to the conflict (b, c) and creating a correct trace (a, b, c) [18]

Жүктеу (53KB)
Метадеректер
5. Fig. 4. Capacitances of extended conductors

Жүктеу (66KB)
Метадеректер
6. Fig. 5. Examples of two-dimensional templates

Жүктеу (50KB)
Метадеректер
7. Fig. 6. Capacities that cannot be taken into account using two-dimensional templates

Жүктеу (73KB)
Метадеректер
8. Fig. 7. Design route without UBD

Жүктеу (118KB)
Метадеректер
9. Fig. 8. Design route with UBD

Жүктеу (99KB)
Метадеректер

© Sazonov V., Erokhin R., Serov V., Sheblaev M., 2025