Development Of Charge Trapping SONOS Memory Cells

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Abstract

In this paper, a process for creating a SONOS memory cell with an improved structure within the CMOS route according to 1.5 μm process standards that can be integrated to silicon photonics is proposed. The resulting memory has a write voltage of 12 V and an erase voltage of –13 V. The write speed is 80 ms. The memory window is more than 3 V with a working window of 2 V.

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About the authors

A. E. Gabdrakhmanov

Institute of Nanotechnology of Microelectronics of the Russian Academy of Sciences

Author for correspondence.
Email: amiro202020@gmail.com
ORCID iD: 0009-0002-1195-0944

process engineer, Design Center "Heterogeneous integration"

Russian Federation, Москва

E. N. Rybachek

Scientific-Manufacturing Complex "Technological Centre"

Email: amiro202020@gmail.com
ORCID iD: 0000-0002-3918-4391

Senior Researcher, Cand. of Eng. (Tech. Scien.)

Russian Federation, Зеленоград, Москва

E. M. Yeganova

Institute of Nanotechnology of Microelectronics of the Russian Academy of Sciences

Email: amiro202020@gmail.com
ORCID iD: 0000-0001-6534-4179

Senior Researcher, Cand. of Eng. (Tech. Scien.), Design Center "Heterogeneous integration"

Russian Federation, Москва

D. V. Ryazantsev

Institute of Nanotechnology of Microelectronics of the Russian Academy of Sciences

Email: amiro202020@gmail.com
ORCID iD: 0000-0001-8051-2425

Senior Researcher, Design Center "Heterogeneous integration"

Russian Federation, Москва

N. V. Komarova

Institute of Nanotechnology of Microelectronics of the Russian Academy of Sciences

Email: amiro202020@gmail.com
ORCID iD: 0000-0002-6148-0971

engineer, Cand. of Eng. (Chem. Scien.), Design Center "Heterogeneous integration"

Russian Federation, Москва

A. E. Kuznetsov

Institute of Nanotechnology of Microelectronics of the Russian Academy of Sciences

Email: amiro202020@gmail.com
ORCID iD: 0000-0002-1333-5294

Senior Researcher, Dr. of Eng. (Tech. Scien.), Design Center "Heterogeneous integration"

Russian Federation, Москва

References

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Supplementary files

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2. Fig. 1. Cross-sectional view of flash memory cell structures: а) floating gate memory cell; b) charge trapping memory cell

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3. Fig.2. Charge trapping memory cell: а)diagram with dielectric gate layer thicknesses and layer material; b) topology of the test structure of the memory cell; c) TEM image of a section of the fabricated structure

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4. Fig.3. Dependences of threshold voltage on the write and erase voltage

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5. Fig.4. Dependence of threshold voltage on writing/erasing duration, for determining writing and erasing speed

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Copyright (c) 2024 Gabdrakhmanov A.E., Rybachek E.N., Yeganova E.M., Ryazantsev D.V., Komarova N.V., Kuznetsov A.E.