FAULT TOLERANT CMOS REALIZATION OF A MINORITY FUNCTION FOR AEROSPACE COMPUTER COMPLEXES

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Introduction. In recent years special attention is paid not only to digital equipment of critical application reli- ability, including aerospace digital computer systems [1; 2], but also to radiation-resistant element basis [3]. The Atmel [4; 5] company is working hard on the creation of radiation-resistant chips. One of ways to ensure radiation resistance is creation of special architecture - RHBD (Ra- diation Hardened By Design). This approach includes triple redundancy (Triple Modular Redundancy, TMR) or majority function. Majority reservation is planted in the FPGA [6] (field-programmable gate array) programmable logic integrated circuits (PLIC) of the VirtexTM series of Xilinx [7-9]. At the same time majority devices (Majority Vote Circuits) on the basis of 3-State buffers (BUFT) and vote devices on minority “Minoriti” (minority function, Minority Vote Circuits) are used. It is specified that vote devices on minority can be realized on the basis of so-called LUT (look up table) which represents ROM - multiplexers which inputs of data fix the given logic func- tion [6]. Synthesis of the fault-tolerant device of vote on minority (Minority Vote Circuits) on CMOS transistors for the purpose of their use without involvement of the logical LUT resources and increase in probability of trou- ble-free (consistent) operation of triplicate digital system arouse interest. Majority element based on 3-state buffers with CMOS implementation of minority voted function. The suggested simplified diagram of CMOS Minority Voted function implementation (1) is represented in fig. 4. Element modeling fig. 7 with three additional inverters in the system of circuitry modeling of National Instruments Electronics Workbench Group [10] confirms operability of the element in compliance with the table of validity fig. 3. Fig. 5 represents modeling of working (single) sets A, B, C. Complexity of LUT [6] taking into account the setting in number of transistors (in connection with restrictions, stated in the Rules of topological design by Mead and Conway [11], n can’t be more than 4) has the following appearance: minority function vote devices. In FPGA VirtexTM of Xilinx [7-9] realization of majority function on PLIC Ln = 2n ×8 + 2n+1 + 2n. (2) contact elements (programmable logical integrated circuit) using 3-state buffers and minority vote devices (Minority) is described (fig. 1, 2). Even if for implementation of minority voting function LUT with n = 3 is used, we receive the following number of transistors: The table of “Minority” (Minority Voted) function validity of three channels A, B, C is suggested in fig. 3. L3 = 23 ×8 + 23+1 + 2 ×3 = 86. (3) Thus the Minority Voted function has the following expression: The suggested implementation is complicated by the complexity of three inverters = 18 transistors, what is more than 4 times as less. However, in case of a minority Z = ABC Ú ABC. (1) voting element failure in one channel, the failure in the other channel will lead to a failure of all triplex system. That is (1) equals one in case of difference of this channel (A, B or C) from two others transfering the out- put of the corresponding buffer to the third state to avoid conflict between signals with two other buffers having identical outputs. Let’s construct CMOS implementation diagram (1). Fault tolerant CMOS realizations of voting minor- ity function. To follow the Rules of topological design by Mead and Conway [11] on the number of sequentially switched on transistors (no more than 4) decomposition of the initial diagram is needed. One of the options is pro- vided in fig. 6. Fig. 1. Majority function implementation using “Minority” diagrams (Minority Voted) in sets 000,001, 010,011 Рис. 1. Реализация мажоритирования с использованием схем «минорити» (Minority Voted) на наборах 000,001, 010,011 Fig. 2. Majority function implementation using “Minority” diagrams (Minority Voted) in sets 100,101, 110,111 Рис. 2. Реализация мажоритирования с использованием схем «минорити» (Minority Voted) на наборах 100,101, 110,111 Fig. 3. The table of “Minority” (Minority Voted) function validity Рис. 3. Таблица истинности функции «минорити» (Minority Voted) Fig. 4. Simplified diagram of CMOS Minority Voted function implementation Рис. 4. Упрощённая КМОП схема реализации функции «минорити» (Minority Voted) а b Fig. 5. Modeling of CMOS implementation of the minority voted element: a - set 100; b - set 011 Рис. 5. Моделирование КМОП реализации элемента голосования по меньшинству: а - на наборе 100; б - на наборе 011 Fig. 6. Decomposition of the simplified CMOS diagram of the “Minority” function realization (Minority Voted) Рис. 6. Декомпозиция упрощённой КМОП схемы реализации функции «минорити» (Minority Voted) Further transistors of the decomposed diagram in compliance with [12; 13] are reserved. Simulation of the element of fig. 6 with transistor reservation and with three Let’s estimate the tripling of the offered element. Un- der voting elements tripling taking into account one addi- tional majority function: additional inverters on some input patterns in the system of circuitry simulation of National Instruments Electronics P = (3× e-2×(18)×l×ta - 2 × e-3×(18)×l×ta )e-(12)×l×ta . (6) 3 Workbench Group is shown in fig. 7. Assessment of probability of failure-free operation CMOS voting on minority function realization. For the Under voting elements tripling taking into account three additional majority functions: Veybull model of refusals [14] applied for the purpose of in time radiation resistance assessment of the buffer without reservation we have probability of failure-free operation: P33 = (3 × e-2×(18)×l×ta - 2 × e-3×(18)×l×ta ) ´ ´ (3× e-2×(12)×l×ta - 2 × e-3×(12)×l×ta ). (7) e-(18)l×ta , (4) Diagrams of failure free operation of minority voting where failure density of one transistor, α-coefficient, 1 £a £ 2 ; t - an operating time in case of radiation. For the offered redundant scheme of the voting minor- ity element the probability of failure-free operation will be presented by expression element probability change without reservation, e-(18)l×ta , of probability of failure-free operation of the offered re- dundant diagram, of the tripled with one majority function P(t)ftm , of the tripled diagram P3 with three majority functions, P , under failure rate l = 10-5 of 1/hour are P(t)ftm = [e -4×l×ta + 4 × e -3×l×ta (1- e -l×ta )]22. (5) 33 represented in fig. 8. а b Fig. 7. Modeling of a failure-free element of vote on minority: a - in set 100; b - in set 011 Рис. 7. Моделирование отказоустойчивого элемента голосования по меньшинству: а - на наборе 100; б - на наборе 011 1 0.96 0.92 0.88 - (18) ×l ×t a 1 0.9 0.8 0.7 - (18) ×l ×t a e P3( t) 0.84 0.8 e P3( t) 0.6 0.5 Pftm(t) 0.76 Pftm(t) 0.4 P33( t) 0.72 0.68 0.64 0.6 0 100 200 300 t P33( t) 0.3 0.2 0.1 0 0 200 400 600 800 t а b Fig. 8. Diagrams of failure-free operation of the buffer without reservation probability change e-(6)l×ta , failure-free operation of the redundant diagram - with transistors titration P(t)ftm , of the triple diagram with one majority function P3, of triple diagram with three majority functions P33 under failure density l = 10-5 of 1/hour: a - in the range from 1 to 0.6; b - in the range of probabilities from 1 to 0 Рис. 8. Графики изменения вероятности безотказной (бессбойной) работы буфера без резервирования e-(6)l×ta , вероятности безотказной (бессбойной) работы резервированной схемы - с расчетверением транзисторов P(t)ftm , троированной схемы P3 с одним мажоритаром, троированной схемы с тремя мажоритарами P33 при интенсивности отказов (сбоев) l = 10-5 1/час; а - в диапазоне от 1до 0,6; б - в диапазоне вероятностей от1 до 0 Conclusion. In FPGA Virtex of Xilinx for the purpose of radiation resistance improvement tripling is used (Triple Module Redundancy - TMR). For the delivery of major- ity signal on FPMT connections “Minority” functions realized in three LUT are used, where the single signal is formed only in case of difference of this input from two others, providing at the buffers output which aren’t in the third state, always 0 or 1 without “mixing”. In the article failure-free CMOS realization of the voting minority element, allowing not to use FPMT logical resources and essentially simplify realization of a majority function on the basis of buffers, are described. The executed modeling in the system of circuitry modeling of National Instruments Electronics Workbench Group has confirmed operability of the scheme offered. The assessment failure-free operation probability con- firms a considerable advantage over the triple diagram. This advantage is observed on the wide range of probabil- ity unlike that of the triple diagram which becomes worse than not redundant already at probability of about 0.88.

Авторлар туралы

S. Tyurin

Perm National Research Polytechnic University

Email: tyurinsergfeo@yandex.ru
29, Komsomolsky Av., Perm, 614990, Russian Federation

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