Extreme silicon wafers thinning and formation of nano TSV for 3D heterogeneous integration

Capa

Citar

Texto integral

Acesso aberto Acesso aberto
Acesso é fechado Acesso está concedido
Acesso é fechado Acesso é pago ou somente para assinantes

Resumo

The article considers the state-of-the art technologies that make it possible to thin silicon wafers to 500 nm and form nano TSV with dimensions of 180x250 nm and a depth of 500 nm.

Palavras-chave

Texto integral

Acesso é fechado

Sobre autores

D. Sukhanov

ООО «Остек-ЭК»

Autor responsável pela correspondência
Email: Sukhanov.d@ostec-group.ru

заместитель технического директора

Rússia

Bibliografia

  1. Суханов Д. Шаг по направлению к квантовой электронике или жизнь микроэлектроники в эпоху постМура // Вектор высоких технологий. 2021. №2 (52). С. 20–25.
  2. Thomas D., Jourdain A. Extreme Si thinning and nano-TSVs to advance 3D heterogeneous integration // Chip Scale Review. 2021. V. 25. No. 1. PP. 34–38.
  3. Jourdain A. et al. Extreme thinning of Si wafers for via-last and multi-wafer stacking applications. – IEEE 68th Electronic Components and Technology Conference (ECTC). 29 May – 01 June 2018.
  4. Jourdain A. et al. Extreme wafer thinning and nano-TSV processing for 3D heterogeneous integration. IEEE 70th Electronic Components and Technology Conference (ECTC) in IEEE ECTC. June 2020.
  5. Van Huylenbroeck S. et al. A highly reliable 1 × 5 μm via-last TSV module. – IEEE International Interconnect Technology Conference (IITC). 2018.

Arquivos suplementares

Arquivos suplementares
Ação
1. JATS XML
2. Fig. 1. Typical structures of devices with micro-TSV (a) and nano-TSV (b) [2]

Baixar (114KB)
3. Fig. 2. The process of extreme thinning to 500 nm after plate-to-plate bonding [2]

Baixar (952KB)
4. Fig. 3. Thickness of the Si and TTV working plate at the stages of the thinning process [2]

Baixar (145KB)
5. Fig. 4. The sequence of the TSV structure formation process: a – alignment of Si-TSV with the lower part of M1, dry etching, stopping at STI; b – deposition of a silicon oxide sleeve (10 nm), etching at the bottom; c – metallization of TSV and Cu CMP; d – formation of BSM1. BS PASS – passivation layer on the back of the plate [2]

Baixar (398KB)
6. Fig. 5. Setting up the nano-TSV etching process and an example after filling with Cu and CMP: a – the etching process using inductively coupled plasma (ICP); b – Bosch process at the initial stage; c – configured Bosch process; d – after filling with Cu and CMP [2]

Baixar (105KB)

Declaração de direitos autorais © Sukhanov D., 2025