Email this article Recent achievements in creating chiplets using bridge interconnects
- Authors: Sukhanov D.1
-
Affiliations:
- ООО «Остек-ЭК»
- Issue: No 9 (2024)
- Pages: 88-94
- Section: Micro and nanostructures
- URL: https://journals.eco-vector.com/1992-4178/article/view/642438
- DOI: https://doi.org/10.22184/1992-4178.2024.240.9.88.94
- ID: 642438
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Abstract
The article considers the various state of the art solutions using bridge interconnects, which allow to significantly reduce the cost and size of chiplet-based systems.
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About the authors
D. Sukhanov
ООО «Остек-ЭК»
Author for correspondence.
Email: Sukhanov.D@ostec-group.ru
заместитель технического директора
Russian Federation, 121467, МоскваReferences
- Lau J.H. (Unimicron Technology Corporation). Recent advances in bridges for chiplets communications // Chip Scale Review. November-December 2023.
Supplementary files
Supplementary Files
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Fig. 1. Integration of 2.5D or 3D IC with TSV interposer (a) and chiplets without TSV interposer (EMIB) (b) [1]
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Fig. 2. Solution with EMIB from Intel [1]
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Fig. 3. Intel's Sapphire Rapids processor [1]
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Fig. 4. DBHi from IBM [1]
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Fig. 5. IBM's DBHi Si Bridge for chiplets on a cavity-less package substrate [1]
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Fig. 6. AMD Instinct™ MI250X Computing Accelerator with Si-Bridge for Chiplets on a Cavity-Free Package Substrate [1]
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Fig. 7. Apple's UltraFusion with a Si bridge for SoC on a cavity-less package substrate [1]
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Fig. 8. TSMC roadmap for CoWoS and CoWoS-L (a) and the number of TSV interposers depending on their size (b) [1]
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Fig. 9. Comparison of CoWoS (a) and CoWoS-L (b) from TSMC [1]
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