电邮这篇文章 Recent achievements in creating chiplets using bridge interconnects
- 作者: Sukhanov D.1
-
隶属关系:
- ООО «Остек-ЭК»
- 期: 编号 9 (2024)
- 页面: 88-94
- 栏目: Micro and nanostructures
- URL: https://journals.eco-vector.com/1992-4178/article/view/642438
- DOI: https://doi.org/10.22184/1992-4178.2024.240.9.88.94
- ID: 642438
如何引用文章
开放存取
##reader.subscriptionAccessGranted##
详细
The article considers the various state of the art solutions using bridge interconnects, which allow to significantly reduce the cost and size of chiplet-based systems.
关键词
全文:
作者简介
D. Sukhanov
ООО «Остек-ЭК»
编辑信件的主要联系方式.
Email: Sukhanov.D@ostec-group.ru
заместитель технического директора
俄罗斯联邦, 121467, Москва参考
- Lau J.H. (Unimicron Technology Corporation). Recent advances in bridges for chiplets communications // Chip Scale Review. November-December 2023.
补充文件
附件文件
动作
1.
JATS XML
2.
Fig. 1. Integration of 2.5D or 3D IC with TSV interposer (a) and chiplets without TSV interposer (EMIB) (b) [1]
下载 (137KB)
3.
Fig. 2. Solution with EMIB from Intel [1]
下载 (194KB)
4.
Fig. 3. Intel's Sapphire Rapids processor [1]
下载 (266KB)
5.
Fig. 4. DBHi from IBM [1]
下载 (329KB)
6.
Fig. 5. IBM's DBHi Si Bridge for chiplets on a cavity-less package substrate [1]
下载 (253KB)
7.
Fig. 6. AMD Instinct™ MI250X Computing Accelerator with Si-Bridge for Chiplets on a Cavity-Free Package Substrate [1]
下载 (302KB)
8.
Fig. 7. Apple's UltraFusion with a Si bridge for SoC on a cavity-less package substrate [1]
下载 (232KB)
9.
Fig. 8. TSMC roadmap for CoWoS and CoWoS-L (a) and the number of TSV interposers depending on their size (b) [1]
下载 (246KB)
10.
Fig. 9. Comparison of CoWoS (a) and CoWoS-L (b) from TSMC [1]
下载 (139KB)
