Some aspects of the development of IC testing and verification methodologies

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详细

With the adoption of ever smaller design rules, the increasing use of 3D designs and heterogenous (with diverse design rules and functionality) multi-chip/multi-chiplet modules, the need for new verification methods arises.

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作者简介

M. Makushin

НОБ «Военные науки и оборонная промышленность» БРЭ

编辑信件的主要联系方式.
Email: journal@electronics.ru

ведущий научный редактор

俄罗斯联邦

参考

  1. Bailey B. Improving Verification Methodologies // Semiconductor Engineering. 2025. February 27ʰᵗ.
  2. Peters L. Making The Most of Test Resources // Semiconductor Engineering. 2025. September 9ʰᵗ.
  3. Foster H. How AI And Connected Workflows Will Close The Verification Bottleneck // Semiconductor Engineering. 2025. March 27ʰᵗ.
  4. Peters L. Automation And AI Improve Failure Analysis // Semiconductor Engineering. 2025. March 11ʰᵗ.
  5. Haley G. E-Beam Inspection Proves Essential For Advanced Nodes // Semiconductor Engineering. 2025. May 8ʰᵗ.

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1. JATS XML
2. Fig. 1. Errors identified at each stage of development.

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3. Fig. 2. The number of successful IS creation projects is declining.

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4. Fig. 3. Locations of hidden defects on the wafer, detected by electron beam inspection tools with a resolution of 5 nm.

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